This invention relates to the control of data processing system resources by a plurality of devices using control masters and control slaves. It relates particularly to a network of devices of varying speeds and capacities where any control master must operate with any control slave for proper utilization of the resources. In a more specific application, it relates to bus control masters and bus control slaves in a system where the bus masters contend for access and control of a bus and, once gained through an arbitration controller, the bus control master and the bus control slave cooperate asynchronously to effect data transfers.
Electronic computer systems usually require that the processor have access to input and output devices for useful functioning. For most efficient operation, such devices operate independently from the central processor. That is, unlike early computer systems where the devices were controlled by the central processing unit, modern design moves the processing function into the device, permitting the central processor and the devices to function simultaneously and independently. At times, however, the devices must access resources shared with other devices and with the central processor. For example, a memory is often a shared resource and is accessed via a system bus. Various processors operate on data stored in the memory and some devices are used to store data from outside the system into the memory for processing while other devices read data from the memory for use outside the system, e.g., printing the results of computation and processing.
To reduce interference with the workings of the processor, a technique known as Direct Memory Access (DMA) is used to enable devices to read from or write to the memory without requiring processor intervention. The address of the data location in memory is stored in the device and used to address the memory during one or more cycles while the central processor and other devices are inhibited from accessing the memory. The DMA process operates as an interrupt procedure, so called because it doesn't always require access to the memory on a regular, periodic basis and interrupts the central system for access asynchronously. Such processes are also called cycle stealing.
All the devices cannot access the memory bus simultaneously because there would be no way to distinguish the separate signals. Therefore, resource requests must be arbitrated in a way that fulfills the requirements of all the devices. The problem of arbitrating multiple requests is covered in the cross-related, co-pending patent application Ser. No. 07/908,931. When a bus master gets control of the bus, a bus control master circuit operates together with a bus control slave at the system resource to perform the associated functions such as read or write from a DMA device to a memory.
Prior art bus control masters and bus control slaves sample the control signals and synchronize them to the local clock on both the leading and the trailing edges. This is a safe approach in that it avoids timing hazards and incorrect responses to false signals.
Such timing hazards are not always a problem in systems having bus control masters and bus control slaves that are designed to cooperate with one another and where there is a limited number of bus control masters and bus control slaves. In a system that comprises such devices of widely varying operating parameters or where the number of such devices are not to be limited in number, timing hazards create problems that have been avoided by synchronizing the leading and trailing edges of the control signals with the local clock, even in systems labelled asynchronous.
The bus control slave response to the deactivation of the signal that selected it is delayed until the asynchronous select signal is aligned with the local clock which takes two clock cycles. The synchronization to the local clock prevents the bus control slave from responding to a subsequent select signal before the slave's internal sequencing logic has completed aligning its clock with the external signal and returned to its initial state.
Similarly, the bus control master delays activating selection of the next bus control slave until the acknowledge signal from the previously selected bus control slave has been deactivated. This prevents the acknowledge signal from a previously selected bus control slave from being mistaken for the acknowledgement of the next select signal.
The synchronization of the trailing edges of the select and acknowledge signals prevents timing hazards and anomalies that can arise because of the differences in speeds among the masters and slaves that are coupled to a single bus. For example, a fast bus control master can overrun a slower bus control slave, causing the bus control master to remain linked with the slower bus control slave when another bus control slave was actually supposed to have been selected. On the other hand, a fast bus control slave can activate an acknowledge signal to an asynchronous select signal before a slow bus control master detected the deactivation of a previous acknowledge signal, leading to a false bus error indication because the deactivation of the synchronized acknowledge signal must comply with the interlock of the bus controls. Therefore, synchronization of the trailing edges as well as the leading edge has been considered necessary.
The prior art solutions to the problems are set forth in the following references.
U.S. Pat. No. 3,886,524 discloses the connection of several bus masters, each with logic circuits to arbitrate among several requests. The priority is self-determined among the bus masters which are connected by a bus of three lines common to all the logic circuits. The bus master having control of the bus transmits an "access granted" signal. This locks out the other bus masters until the controlling bus master has completed its data transfer.
U.S. Pat. No. 3,997,896 uses two cycles for transferring data between a bus master and a bus slave, one cycle for initiating the data transfer and the second for actually transferring the data. To eliminate the delay between the initiation and the transfer of data between the first pair, a second pair of bus master and bus slave can communicate between the first and second cycle of the first pair.
U.S. Pat. No. 4,084,233 discloses communication channels controlled by a processor to send or receive data from various devices, all of which operate from a common system clock to prevent timing hazards and anomalies.
U.S. Pat. No. 4,106,104 describes a common control unit to control access to a bus by several devices. The transfer process of a low priority device can be interrupted to allow higher priority device to use the bus. The connection of the devices to the common control unit is a special arrangement that allows some devices to be connected to both sides of the control unit.
The system of U.S. Pat. No. 4,148,011 uses a busy signal that is coupled to the devices competing for access to the bus. The control logic is distributed among the competing devices with the common busy line. The common busy line avoids timing hazards by holding off the other bus masters while the bus master controlling the bus is transferring data.
U.S. Pat. No. 4,390,969 discloses an asynchronous data transfer system using a four-cycle signal, also known as Return-to-Zero, scheme wherein the request and acknowledge signals do not overlap. To insure stability and to avoid timing hazards, the edges of the signals generate fixed duration pulses that provide time for the circuit states to stabilize. In contrast, the invention uses a two-cycle, also known as Nonreturn-to-Zero, scheme without the delay caused by a fixed duration pulse.
U.S. Pat. No. 4,660,169 discloses an asynchronous daisy chain arrangement that enables a bus master to seize control of the bus when a Bus Acknowledge (Grant) signal is received without incurring any synchronization delay. The bus master inhibits setting synchronization latches to prevent passing the bus grant signal to the next bus master in the chain by delaying the setting of the latches for a short time period before a Local Bus Request Required signal is issued to insure the stability of the bus grant signal passed when the bus master determines its need for the bus. If the bus master requires control of the bus, it continues to delay the synchronization latch setting long enough to complete its seizing control of the bus and to signal the bus arbiter that it has taken control. The invention in this application eliminates the delays in setting the latches as well as eliminates the timing problem that occurs when a limiting number of bus masters is exceeded.
U.S. Pat. No. 4,779,089 describes a system having asynchronous bus masters but using synchronization signals for controlling the bus to avoid timing hazards as described above when the bus master operation is asynchronous.
U.S. Pat. No. 4,803,481 relates to the use of a call line between a master unit and a slave unit, the master unit communicating when the logic levels of a master line and a slave line are at the same level and the slave unit communicating when the logic levels are different. The direct communication requirements limit the types of bus masters and bus slaves that can be used in a single system and precludes the need to avoid timing hazards.
U.S. Pat. No. 4,817,037 shows a system of overlapping bus cycle operations using a protocol that allows a bus slave to indicate to the designated bus master that a new bus master is to be designated for temporary communication. The communication with a different bus master takes place during the communication with the designated bus master. The operations are controlled by signals that synchronize the signals used for the communication process.
U.S. Pat. No. 4,821,170 shows a plurality of host processors with at least two system buses. DMA devices control the bus arbitration and allocate alternate bus clock cycles in response to request to exchange data between a dedicated microprocessor and a high speed bus. The bus clock cycles actually provide synchronous operation.
U.S. Pat. No. 4,847,750 shows still another approach to data acquisition that uses a dual port frame map memory for storing address of DMA devices in sequence. Data is rapidly transferred from various peripheral devices having nonsequential addresses to sequential locations of the computer and vice versa. This arrangement limits the number and speed variations of devices using the system.
U.S. Pat. No. 4,887,262 relates to asynchronous bus masters using messages comprising an arbitration field and a data field. It depends, however, on synchronizing the operation of the bus masters so that its operation is not wholly asynchronous.
The invention to be described herein is designed to be wholly asynchronous in that the clocks of each device are independent from each other and can run at widely varying rates. The number of bus masters and bus slaves is not limited.
In accordance with the invention, an access controller selects a resource controller to access the resource controlled by the resource controller. In response to a select signal, the resource controller allows access to the resource for utilization of the resource and supplies an acknowledge signal to indicate the resource is being utilized. The acknowledge signal is terminated as soon as the utilization is completed but the access controller retains the signal until it is in a stable state and terminates the select signal. The resource controller retains the select signal until it is in an initial state.
The two controllers operate asynchronously with respect to one another but prevent response to false signals by retaining the signals until they are in stable states.
To prevent system hang up, the access controller terminates the select signal after a predetermined time if no acknowledge signal is received. It also inhibits the select signal if it is possible for more than one resource controller to be selected, e.g., if there is a parity error in the select signal.